1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device of a field effect type having a MOS structure. More specifically, the present invention relates to a method of manufacturing a semiconductor device which composes a semiconductor integrated circuit such as a voltage regulator, switching regulator, or a voltage detector, which is used for controlling a power source voltage of a portable device or the like.
2. Description of the Related Art
A conventional technique will be described with reference to FIGS. 3A to 3D. Description will be made of a complementary MOSFET device (CMOS) formed on a single crystalline semiconductor substrate as the conventional technique. First, as shown in FIGS. 3A to 3C, an N-type well 34, a field insulator 33, N-type low concentration impurity regions 39, N-type high concentration impurity regions 41 and 42, P-type high concentration impurity regions 43 and 44, P-type low concentration impurity regions 40, and gate electrodes 36 (for an NMOS and a PMOS) made of N-type polycrystalline silicon doped with phosphorus are formed on a P-type semiconductor substrate 31 by using a conventional manufacturing method for an integrated circuit.
The manufacturing method in detail is as follows. First, BF2+ ions are implanted into a P-type silicon wafer having an impurity concentration of about 1E15/cm3, and the field insulator 33 is formed by a so-called LOCOS method. Further, phosphorus ions are implanted into the P-type silicon wafer, and annealing is performed at 1000xc2x0 C. for 3 to 10 hours. Thus, the phosphorus ions are diffused and distributed again to form the N-type well 34 having an impurity concentration of about 1xc3x971016 cmxe2x88x923.
Thereafter, a gate insulating film (silicon oxide) having a thickness of 20 to 100 nm is formed by a thermal oxidation method, and a polycrystalline silicon film having a thickness of 500 nm and a phosphorus concentration of 1xc3x971021 cmxe2x88x923 is formed by a low pressure CVD method. These films are patterned to form portions 36 serving as the gate electrodes.
Then, the N-type low concentration impurity regions 39 having an impurity concentration of 1xc3x971018 cmxe2x88x923 are formed and pocket regions having an impurity concentration of about 1xc3x97101∂cmxe2x88x923 are optionally formed by an ion implantation method using the portions serving as the gate electrodes and another mask (if necessary). In addition, the P-type low concentration impurity regions 40 having an impurity concentration of 1xc3x971018 cmxe2x88x923 are formed, and pocket regions having an impurity concentration of about 1xc3x971017 cmxe2x88x923 are formed if required.
Next, as shown in FIG. 3C, the N-type high concentration impurity regions 41 and 42, and the P-type high concentration impurity regions 43 and 44 are respectively formed with a space for each of the portions 36 serving as the gate electrodes by an ion implantation method. In any impurity region, the impurity concentration is set to about 1xc3x971021 cmxe2x88x923.
Finally, as in the case where an ordinary integrated circuit is manufactured, a phosphorous glass layer 46 is formed as an interlayer insulating film. For example, a low pressure CVD method is preferably used for the formation of the phosphorous glass layer 46. Monosilane (SiH4), oxygen (O2), and phosphine (PH3) are used as material gases and reacted at 450xc2x0 C. to obtain the phosphorous glass layer 46. Then, holes for electrode formation are formed in the interlayer insulating film and aluminum electrodes 45 are formed therein. Thus, a complementary MOS device shown in FIG. 3D is completed.
With respect to the semiconductor device manufactured by the above-mentioned conventional manufacturing method, in the case of an enhancement type NMOS (hereinafter referred to as an E-type NMOS) having a normal reference threshold voltage of about 0.7 V, the gate electrode is made of polycrystalline silicon having an N+-type. Thus, from a relationship of work functions between the gate electrode and a semiconductor substrate, the channel is a surface channel formed on the surface of the semiconductor substrate. On the other hand, in the case of an enhancement type PMOS (hereinafter referred to as an E-type PMOS) having a normal reference threshold voltage of about xe2x88x920.7 V, from a relationship of work functions between the gate electrode made of an N+-type polycrystalline silicon and an N-well, the channel becomes a buried channel formed somewhat inside the semiconductor substrate than the surface of the semiconductor substrate.
In order to realize a low voltage operation, when a threshold voltage is set to, for example, xe2x88x920.5 V or more in the buried channel E-type PMOS, a subthreshold characteristic as one index for low voltage operation of the MOS transistor is extremely deteriorated. Thus, a leak current at an off state of the PMOS is increased. As a result, since a consumption current during standby of the semiconductor device is markedly increased, there arises a problem in that an application to portable devices represented by a mobile telephone and a portable terminal which are said to increase demand in recent years and to further expand the market in the future is difficult.
On the other hand, as a technical method of making a low voltage operation and a low consumption current as the above objects compatible, a so-called homopolar gate technique in which a conductivity type of the gate electrode of an NMOS is made to be an N-type and a conductivity type of the gate electrode of a PMOS is made to be a P-type is generally known. In this case, both an E-type NMOS transistor and an E-type PMOS transistor are surface channel MOS transistors. Thus, even when a threshold voltage is reduced, extreme deterioration of a subthreshold coefficient is not actualized and both low voltage operation and a low consumption current are enabled.
However, there are the following problems in cost and characteristics. That is, with respect to a homopolar gate CMOS, the gates in both an NMOS and a PMOS are formed to be different polarities in manufacturing steps. Thus, as compared with a CMOS having a gate electrode made of only an N+-polycrystalline silicon unipole, the number of steps is increased and increases in a manufacturing cost and a manufacturing period are caused. Further, with respect to an inverter circuit as a most fundamental circuit element, generally, in order to improve area efficiency, the gates of the NMOS and the PMOS is laid out such that a connection through metal is avoided, using a piece of polycrystalline silicon which is two-dimensionally continued from the NMOS to the PMOS or a polycide structure composed of a laminate of polycrystalline silicon and high melting metallic silicide. However, when the gate is made of polycrystalline silicon as a single layer, it is impractical due to a high impedance of a PN junction in the polycrystalline silicon. Also, when the gate is made of the polycide structure, an N-type impurity and a P-type impurity each are diffused to respective gate electrodes having an inverse conductivity type through the high melting metallic silicide at high speed during a thermal treatment of steps. As a result, a work function is changed and a threshold voltage is unstable.
An object of the present invention is to provide a structure capable of realizing a power management semiconductor device and an analog semiconductor device, in which a low cost, a short manufacturing period, a low voltage operation, and low power consumption are enabled.
Therefore, in order to solve the above-mentioned object, according to the present invention, the following means are adopted.
(1) There is employed a method of manufacturing a semiconductor device of a complementary MOS type including an N-channel MOS transistor and a P-channel MOS transistor comprising the steps of: forming a gate insulating film; nitriding the gate insulating film; performing thermal treatment using an inert gas; forming a gate electrode on the gate insulating film; and introducing a p-type impurity into the gate electrode.
(2) There is employed a method of manufacturing a semiconductor device in which the gate electrode is made of polycrystalline silicon.
(3) There is employed a method of manufacturing a semiconductor device in which the gate electrode has a polycide structure composed of a laminate of polycrystalline silicon, high melting metallic silicide, and an insulating film.
(4) There is employed a method of manufacturing a semiconductor device in which the inert gas is N2.
(5) There is employed a method of manufacturing a semiconductor device in which an annealing temperature using the inert gas is 925xc2x0 C. or higher.
(6) There is employed a method of manufacturing a semiconductor device in which a film thickness of the polycrystalline silicon is in a range of from 2000 xc3x85 to 5000 xc3x85.
(7) There is employed a method of manufacturing a semiconductor device in which in the polycide structure, a film thickness of the polycrystalline silicon is in a range of from 2000 xc3x85 to 4500 xc3x85 and a film thickness of the high melting metallic silicide is in a range of from 500 xc3x85 to 3000 xc3x85.
(8) There is employed a method of manufacturing a semiconductor device in which the step of introducing the P-type impurity is ion implantation.
(9) There is employed a method of manufacturing a semiconductor device in which the step of introducing the P-type impurity includes a step of forming a glass film containing a P-type ion and a step of performing annealing.
(10) There is employed a method of manufacturing a semiconductor device in which the step of introducing the P-type impurity includes a step of forming polycrystalline silicon by a low pressure CVD method in a gas atmosphere containing a P-type ion.